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| author | Reid Tonking <reidt@ti.com> | 2024-11-19 06:02:55 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-12-04 14:30:18 -0600 |
| commit | c9fff93cbe9ded56a7c865ed8ca1456d43357761 (patch) | |
| tree | 96d8f9b1fd0fbe6c0532fa25c01544d22f42a9c1 /drivers/ddr/microchip/ddr2.c | |
| parent | 7fe55182d9263a62e18b450c97bdf0b8031e5667 (diff) | |
arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node
The j7200 SOC has a single DDR controller and hence no need for
configuring the MSMC interleaver. Hence we do not have an explicit node
for MSMC in j7200 DT, unlike j721s2/j784s4.
Also, MSMC clk id is described under A72SS0_CORE0 Device in TISCI
documentation [0].
Considering the above, define the MSMC clk in the a72 node.
[0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device
Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions