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author | Tom Rini <trini@konsulko.com> | 2024-12-04 14:30:25 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-12-04 14:30:25 -0600 |
commit | fe76d868f72e483f71a59639c8aa8f658a313b5d (patch) | |
tree | 514a14ce5c2b15a2abee637d95eefcb5e35ab7e6 /drivers/ddr/microchip/ddr2.c | |
parent | 96bddc81481ca890a14eb3e65f5f3a4c9a4aeb0f (diff) | |
parent | abb2544d890a5d23a8ecc40a902fbf0918eda53a (diff) |
Merge patch series "Add OPP_LOW support for J7200"
Aniket Limaye <a-limaye@ti.com> says:
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM.
- A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW
voltage (though OPP_LOW voltage is recommended to reduce power
consumption).
The actual OPP voltage for the device is read from the efuse and
updated in k3_avs_probe().
The default j7200 devicetree and k3_avs driver set OPP_NOM spec
frequency and voltage.
In the board init file, if K3_OPP_LOW config is enabled, Check if
OPP_LOW AVS voltage read from efuse is valid and update frequency (A72
and MSMC) and voltage (VDD_CPU) as per the OPP_LOW spec.
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
Test logs:
https://gist.github.com/aniket-l/328ad93ed60c2419ed7be9f85e6b6075
- With series applied on master and CONFIG_K3_OPP_LOW enabled in
j7200_evm_r5_defconfig
- Logs shown with and without efuse register programmed for OPP_0
(Errors out if OPP_0 not found, programs OPP_LOW spec if found)
- Voltage update verified using 'i2c md 0x4c 0xe' in u-boot
- Frequency update verified using 'k3conf clock dump' in linux
Link: https://lore.kernel.org/r/20241119003617.1871183-1-a-limaye@ti.com
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions