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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:19 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 12:02:01 +0530 |
| commit | 4d40e82663fe5ed8b65242bc28b3faaf838f5dcc (patch) | |
| tree | e7ef658ef2de12a0a5946b7acbf4666bdaa63576 /drivers/ddr/microchip/ddr2_regs.h | |
| parent | 9ec5ea01277d8a9fdd29e797a9e0923575e5ce9f (diff) | |
mtd: spi-nor-core: Parse xSPI Profile 1.0 table
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_regs.h')
0 files changed, 0 insertions, 0 deletions