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author | Andre Przywara <andre.przywara@arm.com> | 2021-09-03 16:49:16 +0100 |
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committer | Andre Przywara <andre.przywara@arm.com> | 2021-09-14 00:02:10 +0100 |
commit | 0b508ca821d383b2fd68f4b581cf606e329fff36 (patch) | |
tree | ee0b01aa26318e8488be0c22f63d4cfc1bf6b18e /drivers/ddr/microchip/ddr2_timing.h | |
parent | 7958292f5ffa4ecdaaf4c73c6df28006051db6e0 (diff) |
sunxi: mmc: A20: Fix MMC optimisation
Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.
Check for this situation and use a safe minimal FIFO size instead when
we hit this case.
This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(9faae5457f52).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions