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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:10 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 11:57:46 +0530 |
| commit | 1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8 (patch) | |
| tree | 20db2ee21f1220b18fbe7b76189cacacfd5ac663 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | 38b0852b0eab1c5ce18ed8125572ffb0bb6973fd (diff) | |
mtd: spi-nor-core: Fix address width on flash chips > 16MB
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions