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authorJacky Chou <jacky_chou@aspeedtech.com>2024-06-27 14:26:00 +0800
committerLeo Yu-Chi Liang <ycliang@andestech.com>2024-09-11 20:34:31 +0800
commit21d5d5e55be85d70c06c5bad0139837665ed4699 (patch)
tree30d5cdf3140b29f430bc621cf6c4a849fcd385a8 /drivers/ddr/microchip/ddr2_timing.h
parentaa4a03f2e2911ddafd754c55f86daa479aa6e2d2 (diff)
net: ftgmac100: Fixed the cache coherency issues of rx memory
When executing TFTP, the ARP will be replied to after receiving the ARP. U-boot's ARP routine modifies the data in the receive packet in response to the ARP packet and then copies it into the transmit packet. At this point, the received packet cache is inconsistent. It is possible that the cache will perform a writeback action to affect the MAC receiving packets. Avoid the same problem that occurs in other networking protocols. In the free_pkt function, ensure cache and memory consistency. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
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