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| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2022-05-12 04:05:34 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-29 16:00:31 +0200 |
| commit | 248fe9f302df5f20d75a7d88b793db017262d750 (patch) | |
| tree | 642dc7f671ce7af7deca3a61857a43c5c60e38f5 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | bf8dae5fcf400a593d56d5847d8ee62bc4c27855 (diff) | |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations
On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions