diff options
| author | Faiz Abbas <faiz_abbas@ti.com> | 2021-02-04 15:10:54 +0530 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2021-02-04 20:37:57 +0530 |
| commit | 27a87c834fde4442088fb55322162df9d96db228 (patch) | |
| tree | 9cc26145f30c7fc6bd6e58cb80bea1f3dceb2e62 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | a759abf569d4f2a238712485379d23f7a5261992 (diff) | |
mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions