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| author | Weijie Gao <weijie.gao@mediatek.com> | 2024-12-17 16:39:27 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-12-31 10:58:52 -0600 |
| commit | 7562da9454c1a6eff3db3b41c183e03039e855e6 (patch) | |
| tree | dbabc7137a63c4ac0b53859bc4904e02931ffea6 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 (diff) | |
net: mediatek: correct register name of ethsys syscfg1
The SYSCFG0 should be SYSCFG1 according to the programming guide.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions