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| author | Hrushikesh Salunke <h-salunke@ti.com> | 2025-06-16 22:19:29 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-06-26 17:16:40 -0600 |
| commit | 7d70986071ea32b2d496ecfc4f9621e454dc1b75 (patch) | |
| tree | e86c0598d03f99dcde582964954a31176395e9bd /drivers/ddr/microchip/ddr2_timing.h | |
| parent | a4a0edc6046dd5b9ebe24ad72dfcdb43b36f0bd6 (diff) | |
configs: am64x_evm_a53_defconfig: Enable configs for PCI Endpoint mode
TI's AM64x SoC has a single instance of PCIe Controller namely PCIe0
which is a Cadence PCIe Controller. To support PCI Endpoint
functionality with the PCIe0 instance of PCIe, enable the corresponding
configs.
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions