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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2023-09-21 12:39:29 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-10-04 17:59:43 +0800 |
| commit | ef5ccaae64b670bc3183e20378d1fa31c86c9f44 (patch) | |
| tree | 96efcedb613d25b83d5a2fbd30b1aa7ce50a44b8 /drivers/ddr/microchip/ddr2_timing.h | |
| parent | f2e4b9d3c2f858f5ce7e317b2974d74353abb2a2 (diff) | |
cmd/exception: test RISC-V 16 bit aligned instruction
A 16 bit aligned instruction should generated an exception if the C
extension is not available.
Provide an 'extension ialign16' command for testing exception handling.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception ialign16
Unhandled exception: Instruction address misaligned
EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions