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| author | Tom Rini <trini@konsulko.com> | 2023-04-14 10:50:55 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-04-14 10:50:55 -0400 |
| commit | 12c1e5782401abca1a8cff578d1911a9ca7d2e7d (patch) | |
| tree | 90cd274dba3b3e0191d63220abd33df99ca078c0 /drivers/ddr | |
| parent | 75f415b3269891984d4bc87ba411173901763613 (diff) | |
| parent | 6add83991b2887619d0b25e4068b4c0082a4596a (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Boot support for 4K Native disks (Pali)
- a38x: Perform DDR training sequence again for 2nd boot (Tony)
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 6e7949ac72c..8ec9fb0874e 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -1363,13 +1363,6 @@ int mv_ddr_pre_training_soc_config(const char *ddr_type) DRAM_RESET_MASK_MASKED << DRAM_RESET_MASK_OFFS); } - /* Check if DRAM is already initialized */ - if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & - (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) { - printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); - return MV_OK; - } - /* Fix read ready phases for all SOC in reg 0x15c8 */ reg_val = reg_read(TRAINING_DBG_3_REG); |