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| author | Tom Rini <trini@konsulko.com> | 2022-08-04 16:53:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 16:54:01 -0400 |
| commit | b8e09898919e23c5d7f1934be7bf9a3a6f0deb0e (patch) | |
| tree | ba1c168b729947aec2a487791e5a26ce72da4282 /drivers/ddr | |
| parent | 62e6418031bed3671e57e63d49273e2739a82589 (diff) | |
| parent | 78475d2572615471d3c047e61481a68859d0dd7f (diff) | |
Merge branch '2022-08-04-Kconfig-migrations'
- Further migrations to Kconfig and associated dead code removal.
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index d93ed8d2feb..22400a9b8ba 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING timing parameters are extracted from datasheet and hard-coded into header files or board specific files. +config SYS_FSL_DDR_INTLV_256B + bool "Enforce 256-byte interleave" + help + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape SoCs + with ARM core. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" |