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| author | Michael Walle <mwalle@kernel.org> | 2024-05-13 22:56:08 +0200 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2024-07-15 22:18:16 +0100 |
| commit | f06757324b2f2b0e062113a51f517a5361e6603c (patch) | |
| tree | d65bba782032e9789ca6f55e1a2744094272ce94 /drivers/firmware/psci.c | |
| parent | cee40d66a6924b9e40c9ece9cfb468d19a721144 (diff) | |
clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC
Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/firmware/psci.c')
0 files changed, 0 insertions, 0 deletions