Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation

1 files changed, 1 insertions, 3 deletions

diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index e0d66d74f54..23cf807591c 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -67,11 +67,9 @@ static int psci_bind(struct udevice *dev)
 
 static int psci_probe(struct udevice *dev)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	const char *method;
 
-	method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev), "method",
-				    0, NULL);
+	method = ofnode_read_string(dev_ofnode(dev), "method");
 	if (!method) {
 		pr_warn("missing \"method\" property\n");
 		return -ENXIO;