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authorChee Hong Ang <chee.hong.ang@intel.com>2020-07-10 20:55:22 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2020-10-09 17:53:10 +0800
commit35d847ed908d3b1d6e58d95b3b9f326111343df5 (patch)
tree1b164cdf0ab1fbfbbf8145342030ab1d313b2288 /drivers/fpga/altera.c
parentd3e829b6183a857b9f5b7626ae6af2eaff95c555 (diff)
clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot mode' before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Diffstat (limited to 'drivers/fpga/altera.c')
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