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authorMichal Simek <michal.simek@amd.com>2022-11-06 11:48:06 -0800
committerMichal Simek <michal.simek@amd.com>2022-11-22 15:02:07 +0100
commit9dc51069f4dfc64f8b86565239c46995aad09dec (patch)
tree8dd93a245ba6f5c868f216a322f7b423bcf8140e /drivers/fpga/altera.c
parent6b067f4bfacb9e57423d0b15a343abe51ca3fff8 (diff)
xilinx: versal-net: Fix SYS_LOAD_ADDR to point to OCM
Versal NET mini U-Boot configuration is used for memory testing that's why load address can't be really placed in memory which doesn't need to work that's why move it to start of OCM which is the same memory which U-Boot is running from. Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/fpga/altera.c')
0 files changed, 0 insertions, 0 deletions