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authorChin Liang See <chin.liang.see@intel.com>2020-08-05 18:34:33 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2020-10-09 17:53:11 +0800
commitf833d6a4ce5ba890eadcae1846c59812478e909c (patch)
treeb9be95c2008f1ab8ab7f4e294ae66344d1961292 /drivers/fpga/altera.c
parent12cc44884b0e74260c2f7396b993f178f8c8df27 (diff)
configs: socfpga: soc64: Avoid SPL enter infinite loop during exception
In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/fpga/altera.c')
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