diff options
author | Tom Rini <trini@konsulko.com> | 2022-10-11 09:57:08 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2022-10-11 09:57:08 -0400 |
commit | 300077cf8cfe6875f3f0a919ec1d0dd32c42b178 (patch) | |
tree | b2298def2119bcb893965610b4b8575d89a4cc15 /drivers/fpga/cyclon2.c | |
parent | 20be7c19a2d6d4a994c40c014ae53b39bdcfacf1 (diff) | |
parent | 63c46e028c14254f28332b3bd57fc3202e26b10a (diff) |
Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.01-rc1 (round 3)
fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure
zynq:
- Enable early EEPROM decoding
- Some DT updates
zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates
net:
- emaclite: Enable driver for RISC-V
xilinx:
- Fix static checker warnings
- Fix GCC12 warning
sdhci:
- Read PD id from DT
Diffstat (limited to 'drivers/fpga/cyclon2.c')
-rw-r--r-- | drivers/fpga/cyclon2.c | 38 |
1 files changed, 16 insertions, 22 deletions
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 3b008facb8c..f264ff8c0ec 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -5,18 +5,14 @@ * Based on ACE1XK.c */ +#define LOG_CATEGORY UCLASS_FPGA + #include <common.h> /* core U-Boot definitions */ +#include <log.h> #include <altera.h> #include <ACEX1K.h> /* ACEX device family */ #include <linux/delay.h> -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt, args...) printf(fmt, ##args) -#else -#define PRINTF(fmt, args...) -#endif - /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). * If there is a need to operate slower, define CONFIG_FPGA_DELAY in @@ -42,7 +38,7 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF("%s: Launching Passive Serial Loader\n", __func__); + log_debug("Launching Passive Serial Loader\n"); ret_val = CYC2_ps_load(desc, buf, bsize); break; @@ -51,8 +47,7 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) * done in the write() callback. Use the existing PS load * function for FPP, too. */ - PRINTF("%s: Launching Fast Passive Parallel Loader\n", - __func__); + log_debug("Launching Fast Passive Parallel Loader\n"); ret_val = CYC2_ps_load(desc, buf, bsize); break; @@ -72,7 +67,7 @@ int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF("%s: Launching Passive Serial Dump\n", __func__); + log_debug("Launching Passive Serial Dump\n"); ret_val = CYC2_ps_dump(desc, buf, bsize); break; @@ -99,22 +94,21 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; int ret = 0; - PRINTF("%s: start with interface functions @ 0x%p\n", - __func__, fn); + log_debug("start with interface functions @ 0x%p\n", fn); if (fn) { int cookie = desc->cookie; /* make a local copy */ unsigned long ts; /* timestamp */ - PRINTF("%s: Function Table:\n" - "ptr:\t0x%p\n" - "struct: 0x%p\n" - "config:\t0x%p\n" - "status:\t0x%p\n" - "write:\t0x%p\n" - "done:\t0x%p\n\n", - __func__, &fn, fn, fn->config, fn->status, - fn->write, fn->done); + log_debug("Function Table:\n" + "ptr:\t0x%p\n" + "struct: 0x%p\n" + "config:\t0x%p\n" + "status:\t0x%p\n" + "write:\t0x%p\n" + "done:\t0x%p\n\n", + &fn, fn, fn->config, fn->status, + fn->write, fn->done); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK printf("Loading FPGA Device %d...", cookie); #endif |