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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2024-01-23 19:16:23 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2024-04-21 09:07:01 +0200 |
| commit | 8c0eb06fbe2cc9bca76a54c861852165c4888963 (patch) | |
| tree | d11d82740e4bc6859d9142d95c174908a12bd94c /drivers/fpga/fpga-uclass.c | |
| parent | 8a8bfd8c137ced359958b8409b73d7f72466b89d (diff) | |
video: tegra20: dc: configure behavior if PLLD/D2 is used
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated from the
original PLLD/D2 frequency and is passed from the DSI driver.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Ion Agorria <ion@agorria.com> # HTC One X
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Microsoft Surface 2
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/fpga/fpga-uclass.c')
0 files changed, 0 insertions, 0 deletions