Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.01-rc2-v2

fpga:
- Enable loading bitstream via fit image for !xilinx platforms

zynq:
- Fix SPL SD boot mode

zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues

test:
- Fix env test for !hush case - Stephen's patch

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index e0fb1b4e783..6aead27f162 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -171,6 +171,15 @@ int fpga_add(fpga_type devtype, void *desc)
 }
 
 /*
+ * Return 1 if the fpga data is partial.
+ * This is only required for fpga drivers that support bitstream_type.
+ */
+int __weak fpga_is_partial_data(int devnum, size_t img_len)
+{
+	return 0;
+}
+
+/*
  * Convert bitstream data and load into the fpga
  */
 int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,