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authorAndre Przywara <andre.przywara@arm.com>2022-05-03 02:06:37 +0100
committerAndre Przywara <andre.przywara@arm.com>2022-07-18 11:27:59 +0100
commitfcd6d936aac7bd934d125135a71192e3a3da9b48 (patch)
treeca7bb625ec767c0bfb357fe4324dd6280e1c2a37 /drivers/fpga/ivm_core.c
parent239dfd11764ac59a3f413c7f5d7575bcebd34228 (diff)
spi: sunxi: improve SPI clock calculation
The current SPI clock divider calculation has two problems: - We use a normal round-down division, which results in a divider typically being too small, resulting in a too high frequency on the bus. - The calculaction for the power-of-two divider is very inaccurate, and again rounds down, which might lead to wild bus frequencies. This wasn't a real problem so far, since most chips can handle slightly higher bus frequencies just fine. Also the actual speed was mostly lost anyway, due to release_bus() reseting the device. And the power-of-2 calculation was probably never used, because it only applies to frequencies below 47 KHz. However this will become a problem for the F1C100s support, due to its much higher base frequency. Calculate a safe divider correctly (using round-up), and re-use that value when calculating the power-of-2 value. We also separate the maximum frequency and the input clock on the way, since they will be different for the F1C100s. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/fpga/ivm_core.c')
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