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authorAndre Przywara <andre.przywara@arm.com>2023-11-05 11:01:42 +0000
committerAndre Przywara <andre.przywara@arm.com>2025-01-22 22:44:34 +0000
commitb002ce88a9f97803341b03a71c374f762e9cd8cd (patch)
tree28d22a18f638db04cb441f81e78ff9ee1427b319 /drivers/fpga/stratixv.c
parent2eed5a1ff36217372e19f7513bd07077fc76718a (diff)
sunxi: clock: improve grouping of default clock register values
With each new SoC added to the clock_sun50i_h6.h header file, we add a list of default values for the bus clock registers. This list gets a bit hard to read, as the spacing between the lines looks confusing. Tighten the lines by removing empty lines, to make it more obvious which values belong together. Also remove those comments that were more or less duplicating the next code line, and didn't add any information. This makes it easier to find existing values and to add support for new SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Diffstat (limited to 'drivers/fpga/stratixv.c')
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