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authorAndrew Goodbody <andrew.goodbody@linaro.org>2025-07-23 17:04:41 +0100
committerMinkyu Kang <mk7.kang@samsung.com>2025-09-01 16:37:08 +0900
commitc901732558fbee5b798bb7a065f7832d3a6bbc84 (patch)
tree16c2067dd66fb923a3bb6fa25636a92dd45eecd3 /drivers/fpga/stratixv.c
parent3dc5e9a0108bb114175b6362f9cb22367402f624 (diff)
clk: exynos: Fix always true test
In exynos7420_peric1_get_rate the variable ret is declared as an 'unsigned int' but is then used to receive the return value of clk_get_by_index which returns an int. The value of ret is then tested for being less than 0 which will always fail for an unsigned variable. Fix this by declaring ret as an 'int' so that the test for the error condition is valid. This issue was found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'drivers/fpga/stratixv.c')
0 files changed, 0 insertions, 0 deletions