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| author | Tom Rini <trini@konsulko.com> | 2020-08-20 14:46:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-08-20 14:46:43 -0400 |
| commit | 2e6132d835631946b7a67dedd8f5bc902304b0f9 (patch) | |
| tree | 5f2a36b99365328bb2b5003d6059de1c74f536d2 /drivers/fpga/versalpl.c | |
| parent | 2a4484a5c54cd64d5c4f8fd9aaa56f739d1b2b9d (diff) | |
| parent | 29af2ac48c8f910cc2efc8099323f9d619fb2bd5 (diff) | |
Merge tag 'xilinx-for-v2020.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2020.10-rc3
- Fix fdtfile variable setup
- Fix bootm_*/fdt_high/initrd_high variables handling
- Fix Kconfig dependencies for Xilinx drivers
- Fix booting u-boot from lowest memory
- Fix firmware payload argument count for Versal
- Fix dfu configurations
- Fix mio_bank property handling
- Fix and align code around ID detection
- Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG
- Simplify logic around reading MAC from eeprom
- Decrease malloc length for zynqmp mini qspi
- Enable preboot for ZynqMP and Versal
i2c:
- Fix i2c eeprom partitions handling
mmc:
- Fix logic around HS mode enabling and use proper functions
Diffstat (limited to 'drivers/fpga/versalpl.c')
| -rw-r--r-- | drivers/fpga/versalpl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 8e2ef4f0da9..c44a7d34557 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -32,7 +32,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, ulong bin_buf; int ret; u32 buf_lo, buf_hi; - u32 ret_payload[5]; + u32 ret_payload[PAYLOAD_ARG_CNT]; bin_buf = versal_align_dma_buffer((ulong *)buf, bsize); |