diff options
| author | Tom Rini <trini@konsulko.com> | 2019-10-25 11:23:46 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-25 11:23:46 -0400 |
| commit | e382713d224d6fc14cf8fe8f6bb852f24ab652a7 (patch) | |
| tree | 132e3dcd8c2ab9ae7b7e5e114216f0f52b13766c /drivers/fpga/versalpl.c | |
| parent | 17fd9915a4c639381804ed28274fa136ae3b0bee (diff) | |
| parent | 3ad95ed6f87de048861ea8b9c3ab9a77e548d7b1 (diff) | |
Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2020.01 part 2
common:
- Fix manual relocation for repeatable commands
arm:
- Also clean up generated dtbos
microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support
zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()
zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216
versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration
spi:
- gqspi - Remove unused headers
Diffstat (limited to 'drivers/fpga/versalpl.c')
| -rw-r--r-- | drivers/fpga/versalpl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 69617a9b1d7..4bcc2132432 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -8,6 +8,7 @@ #include <asm/arch/sys_proto.h> #include <memalign.h> #include <versalpl.h> +#include <zynqmp_firmware.h> static ulong versal_align_dma_buffer(ulong *buf, u32 len) { @@ -38,7 +39,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits(bin_buf); buf_hi = upper_32_bits(bin_buf); - ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, buf_hi, 0, ret_payload); if (ret) puts("PL FPGA LOAD fail\n"); |