diff options
| author | Tom Rini <trini@konsulko.com> | 2022-12-23 22:19:39 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-12-23 22:19:39 -0500 |
| commit | 3e4cbe184a0f6537abb457d6afa61224396c4e46 (patch) | |
| tree | d6e95e03385c33f5d99775cc44710fc6f540b094 /drivers/fpga/virtex2.c | |
| parent | 52d91e1c20b399ddab276e2c03e5788ed5e5fdd2 (diff) | |
| parent | 90c7888c9d6b3223c32f068668f3bc5a81010f8e (diff) | |
Merge branch '2022-12-23-complete-phase1-CONFIG-migration' into next
- Bring in the final series to complete the main portion of migrating
CONFIG symbols to either Kconfig or CFG namespace (or removing /
renaming entirely). With this, we have stricter CI tests as well now.
Diffstat (limited to 'drivers/fpga/virtex2.c')
| -rw-r--r-- | drivers/fpga/virtex2.c | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8871deaea6f..fc99a5f4831 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -21,17 +21,14 @@ #include <linux/delay.h> /* - * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * If the SelectMap interface can be overrun by the processor, enable + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_SYS_FPGA_CHECK_BUSY -#undef CONFIG_SYS_FPGA_CHECK_BUSY -#endif -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif /* @@ -199,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) } while (!(*fn->init)(cookie)); (*fn->pgm)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->clk) (*fn->clk)(true, true, cookie); @@ -208,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) */ ts = get_timer(0); do { - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); @@ -236,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, /* * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->cs) (*fn->cs)(false, true, cookie); if (fn->wr) @@ -272,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, (*fn->wbulkdata)(&dummy, 1, true, cookie); } else { (*fn->wdata)(0xff, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } } @@ -338,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif (*fn->wdata)(data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); /* * Cycle the clock pin */ (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -475,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) for (bit = 7; bit >= 0; --bit) { unsigned char curr_bit = (curr_data >> bit) & 1; (*fn->wdata)(curr_bit, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } |