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| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2022-11-23 02:04:51 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-12-05 08:55:54 +0100 |
| commit | a5e770b21ccc4d3ffc5cf50cab481cb0e35ee6ce (patch) | |
| tree | a57ba961198686019431e10a9c08065c588b8337 /drivers/fpga/xilinx.c | |
| parent | d9efdc7d424ddfdc2aafeee4268435f9f46dd1db (diff) | |
spi: zynqmp_gqspi: Update tapdelay value
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1
tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1
based on the recommended value in IP spec.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/fpga/xilinx.c')
0 files changed, 0 insertions, 0 deletions