diff options
| author | Simon Glass <sjg@chromium.org> | 2024-09-29 19:49:48 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-11 11:44:48 -0600 |
| commit | 371dc068bbf50c6ed6146c04ec83b644bcc79249 (patch) | |
| tree | edad3a36155bccf380c703c2c81e2c0a9ab210a4 /drivers/fpga | |
| parent | dac3ce976a9b06be5aadbd857c4b64a8c521c6d4 (diff) | |
drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Use the new symbol to refer to any 'SPL' build, including TPL and VPL
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/intel_sdm_mb.c | 2 | ||||
| -rw-r--r-- | drivers/fpga/zynqpl.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 45caef4f5c1..5a65bd98779 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -17,7 +17,7 @@ #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) #define BITSTREAM_CHUNK_SIZE 0xFFFF0 #define RECONFIG_STATUS_POLL_RETRY_MAX 100 diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 57467b4d975..3e86d854a01 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -414,13 +414,13 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) puts("INFO:post config was not run, please run manually if needed\n"); return FPGA_SUCCESS; } -#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD) static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, fpga_fs_info *fsinfo) { @@ -504,7 +504,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, struct xilinx_fpga_op zynq_op = { .load = zynq_load, -#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD) .loadfs = zynq_loadfs, #endif }; |