socfpga_agilex5: config: Relocate malloc and bss address

With Inline ECC enabled, the bottom 1/8 of DDR is reserved
for ECC parity bits and must not be used for general data address
allocation. Previously, the SPL bss and malloc addresses were allocated
inside this ECC parity region if the DDR size is 1GB.

This caused ECC hardware to detect stale or invalid parity bits,
leading to data correction attempts and DMA polling hangs or failures.

Fix this by relocating the malloc and bss to the usable 7/8 region of DDR
and is fully ECC-safe.

This change ensures reliable ddr address operation and
prevents unintended memory corruption.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

0 files changed, 0 insertions, 0 deletions