Merge branch 'next'

Bring in the following merges:

commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87
Merge: 87f69f467a83 63618e71e89b
Author: Tom Rini <trini@konsulko.com>
Date:   Fri Jan 3 09:48:47 2020 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

    - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support

commit 87f69f467a8335b171c71bf217d2625d515acd7c
Merge: c0912f9bbfb2 4466b9970319
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 24 08:18:19 2019 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next

    - Enable DM driver on ppc/km boards
    - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
      T104x, P4080, P2041, P2020, P1020, P3041
    - Some updates in mpc85xx-ddr driver, km boards

commit c0912f9bbfb26dd03d189953678691b799d35b6e
Merge: 533c9f5714bd a1d6dc3f8407
Author: Tom Rini <trini@konsulko.com>
Date:   Wed Dec 18 07:20:19 2019 -0500

    Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

    - Various x86 common codes updated for TPL/SPL
    - I2C designware driver updated for PCI
    - ICH SPI driver updated to support Apollo Lake
    - Add Intel FSP2 base support
    - Intel Apollo Lake platform specific drivers support
    - Add a new board Google Chromebook Coral

commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1
Merge: 553cb0688782 033e18b47bd0
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 17 07:53:08 2019 -0500

    Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

    i2c: for next
    - misc: i2c_eeprom:
      Add partition support and add ability to query size
      of eeprom device and partitions
    - i2c common:
      add support for offset overflow in to address and add
      sandbox tests for it.

commit 553cb06887825314e74a9bdac337467c77d1db88
Merge: f39abbbc531e b4f98b3b16ec
Author: Tom Rini <trini@konsulko.com>
Date:   Thu Dec 12 08:18:59 2019 -0500

    Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next

    buildman improvements including toolchain environment feature
    sandbox unicode support in serial

1 files changed, 144 insertions, 0 deletions

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
new file mode 100644
index 00000000000..7f0625df66b
--- /dev/null
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Copyright 2019 Google Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <asm/lpss.h>
+#include "designware_i2c.h"
+
+enum {
+	VANILLA		= 0,	/* standard I2C with no tweaks */
+	INTEL_APL,		/* Apollo Lake I2C */
+};
+
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+	.ss_hcnt = 0x200,
+	.fs_hcnt = 0x55,
+	.ss_lcnt = 0x200,
+	.fs_lcnt = 0x99,
+	.sda_hold = 0x6,
+};
+
+/* Have a weak function for now - possibly should be a new uclass */
+__weak void lpss_reset_release(void *regs);
+
+static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
+{
+	struct dw_i2c *priv = dev_get_priv(dev);
+
+	if (spl_phase() < PHASE_SPL) {
+		u32 base;
+		int ret;
+
+		ret = dev_read_u32(dev, "early-regs", &base);
+		if (ret)
+			return log_msg_ret("early-regs", ret);
+
+		/* Set i2c base address */
+		dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
+
+		/* Enable memory access and bus master */
+		dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+				      PCI_COMMAND_MASTER);
+	}
+
+	if (spl_phase() < PHASE_BOARD_F) {
+		/* Handle early, fixed mapping into a different address space */
+		priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
+	} else {
+		priv->regs = (struct i2c_regs *)
+			dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+	}
+	if (!priv->regs)
+		return -EINVAL;
+
+	/* Save base address from PCI BAR */
+	if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
+		/* Use BayTrail specific timing values */
+		priv->scl_sda_cfg = &byt_config;
+
+	return 0;
+}
+
+static int designware_i2c_pci_probe(struct udevice *dev)
+{
+	struct dw_i2c *priv = dev_get_priv(dev);
+
+	if (dev_get_driver_data(dev) == INTEL_APL) {
+		/* Ensure controller is in D0 state */
+		lpss_set_power_state(dev, STATE_D0);
+
+		lpss_reset_release(priv->regs);
+	}
+
+	return designware_i2c_probe(dev);
+}
+
+static int designware_i2c_pci_bind(struct udevice *dev)
+{
+	char name[20];
+
+	/*
+	 * Create a unique device name for PCI type devices
+	 * ToDo:
+	 * Setting req_seq in the driver is probably not recommended.
+	 * But without a DT alias the number is not configured. And
+	 * using this driver is impossible for PCIe I2C devices.
+	 * This can be removed, once a better (correct) way for this
+	 * is found and implemented.
+	 *
+	 * TODO(sjg@chromium.org): Perhaps if uclasses had platdata this would
+	 * be possible. We cannot use static data in drivers since they may be
+	 * used in SPL or before relocation.
+	 */
+	dev->req_seq = gd->arch.dw_i2c_num_cards++;
+	sprintf(name, "i2c_designware#%u", dev->req_seq);
+	device_set_name(dev, name);
+
+	return 0;
+}
+
+static const struct udevice_id designware_i2c_pci_ids[] = {
+	{ .compatible = "snps,designware-i2c-pci" },
+	{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
+	{ }
+};
+
+U_BOOT_DRIVER(i2c_designware_pci) = {
+	.name	= "i2c_designware_pci",
+	.id	= UCLASS_I2C,
+	.of_match = designware_i2c_pci_ids,
+	.bind	= designware_i2c_pci_bind,
+	.ofdata_to_platdata	= designware_i2c_pci_ofdata_to_platdata,
+	.probe	= designware_i2c_pci_probe,
+	.priv_auto_alloc_size = sizeof(struct dw_i2c),
+	.remove = designware_i2c_remove,
+	.flags = DM_FLAG_OS_PREPARE,
+	.ops	= &designware_i2c_ops,
+};
+
+static struct pci_device_id designware_pci_supported[] = {
+	/* Intel BayTrail has 7 I2C controller located on the PCI bus */
+	{ PCI_VDEVICE(INTEL, 0x0f41) },
+	{ PCI_VDEVICE(INTEL, 0x0f42) },
+	{ PCI_VDEVICE(INTEL, 0x0f43) },
+	{ PCI_VDEVICE(INTEL, 0x0f44) },
+	{ PCI_VDEVICE(INTEL, 0x0f45) },
+	{ PCI_VDEVICE(INTEL, 0x0f46) },
+	{ PCI_VDEVICE(INTEL, 0x0f47) },
+	{ PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
+	{ PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
+	{ PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
+	{ PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
+	{ PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
+	{ PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
+	{},
+};
+
+U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);