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| author | Tom Rini <trini@konsulko.com> | 2024-08-09 08:22:32 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-09 08:22:32 -0600 |
| commit | 37ce540fe451a8b7a94155c170f7d3084adecb1e (patch) | |
| tree | 27b7bb492e6196a54cd19b7d4f5879a0e7e1f65f /drivers/i2c/exynos_hs_i2c.c | |
| parent | 1c5445f190cabfd0e453f583aca44da10156c0d6 (diff) | |
| parent | ec07bcc8eafb8d201d15facc969fe96600660095 (diff) | |
Merge tag 'i2cfixes-v2-for-v2024-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2024.10-rc3 (second try)
- i2c: samsung: Support platforms other than EXYNOS4 and EXYNOS5
from David
- imx_lpi2c: cleanups and support read transfers longer than 256 bytes
from Fedor
- pca954x: Remove pointer to GD
from Michal
- i2c: mux: Fix error path in i2c-arb-gpio
from Michal
Diffstat (limited to 'drivers/i2c/exynos_hs_i2c.c')
| -rw-r--r-- | drivers/i2c/exynos_hs_i2c.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 2ab0bae4499..fa0d1c8f64a 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -9,11 +9,15 @@ #include <dm.h> #include <i2c.h> #include <log.h> +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) #include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/pinmux.h> +#endif #include <asm/global_data.h> +#include <asm/io.h> #include <linux/delay.h> +#include <clk.h> #include "s3c24x0_i2c.h" DECLARE_GLOBAL_DATA_PTR; @@ -137,18 +141,25 @@ static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) return I2C_NOK_TOUT; } -static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) +static int hsi2c_get_clk_details(struct udevice *dev) { + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; ulong clkin; unsigned int op_clk = i2c_bus->clock_frequency; unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; -#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) clkin = get_i2c_clk(); #else - clkin = get_PCLK(); + struct clk clk; + int ret; + + ret = clk_get_by_name(dev, "hsi2c", &clk); + if (ret < 0) + return ret; + clkin = clk_get_rate(&clk); #endif /* FPCLK / FI2C = * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE @@ -491,7 +502,7 @@ static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) i2c_bus->clock_frequency = speed; - if (hsi2c_get_clk_details(i2c_bus)) + if (hsi2c_get_clk_details(dev)) return -EFAULT; hsi2c_ch_init(i2c_bus); @@ -518,7 +529,9 @@ static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) static int s3c_i2c_of_to_plat(struct udevice *dev) { +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) const void *blob = gd->fdt_blob; +#endif struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); int node; @@ -526,7 +539,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->hsregs = dev_read_addr_ptr(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) i2c_bus->id = pinmux_decode_periph_id(blob, node); +#endif i2c_bus->clock_frequency = dev_read_u32_default(dev, "clock-frequency", @@ -534,7 +549,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->node = node; i2c_bus->bus_num = dev_seq(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); +#endif i2c_bus->active = true; |