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authorTom Rini <trini@konsulko.com>2025-06-14 09:10:48 -0600
committerTom Rini <trini@konsulko.com>2025-06-14 09:10:48 -0600
commit03817a2a8046ea89dac2be72ce0c16a9faa5570b (patch)
treeb4d6f39f9b0ded094c7f54aeb135a9eae6e19492 /drivers/mmc
parent2556caa89caba6c3d4df7910828119bc65beb1f0 (diff)
parent0230ad1c30a405c807dad5f78c95c57704234ffd (diff)
Merge patch series "Hex value prefix case cleanup"
E Shattow <e@freeshell.de> says: Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot. There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix or placeholder in documentation and error messages. External devicetree-rebasing dts/upstream and the generated code of xilinx/zynq are ignored for the series. Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/sdhci-cadence6.c2
-rw-r--r--drivers/mmc/zynq_sdhci.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c
index a5ed87321ab..9a92b8437a6 100644
--- a/drivers/mmc/sdhci-cadence6.c
+++ b/drivers/mmc/sdhci-cadence6.c
@@ -19,7 +19,7 @@
#include "sdhci-cadence.h"
/* IO Delay Information */
-#define SDHCI_CDNS_HRS07 0X1C
+#define SDHCI_CDNS_HRS07 0x1C
#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16)
#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 0e2bdab4e7e..2375b15539b 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -83,7 +83,7 @@
#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39
#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146
-#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
+#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0x77
struct arasan_sdhci_clk_data {
int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];