diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-20 08:08:29 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-20 08:08:29 -0400 |
| commit | a9e90d357bbf539e07c1d971161e027eb335183e (patch) | |
| tree | c0994366667aa4acdd55b8e5054d83a0560eb8a2 /drivers/mmc | |
| parent | 98c4828740f4944462b7d9608b95d5b73850c7b0 (diff) | |
| parent | 7bc683afda5ede82cfcace77cecab1891d6d93ff (diff) | |
Merge tag 'fsl-qoriq-2022-6-20-v2' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Layerscape:
add sfp driver
Kconfig cleanup
sl28 board update
support hdp firmware loading
powerpc:
dts update for p2020
p1_p2_rdb_pc board update
fsl_esdhc fallback to 1-bit mode support
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/Kconfig | 5 | ||||
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c8f9709d2d4..5a87db6be08 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -839,6 +839,11 @@ config FSL_ESDHC_VS33_NOT_SUPPORT For eSDHC, power supply is through peripheral circuit. 3.3V support is common. Select this if 3.3V power supply not supported. +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + int + depends on FSL_ESDHC + default 1 + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fdf2cc290e0..4e7bfdfaa7e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -946,9 +946,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) } else if (cfg->max_bus_width == 1) { mmc_cfg->host_caps |= MMC_MODE_1BIT; } else { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | - MMC_MODE_8BIT; - printf("No max bus width provided. Assume 8-bit supported.\n"); + mmc_cfg->host_caps |= MMC_MODE_1BIT; + printf("No max bus width provided. Fallback to 1-bit mode.\n"); } if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK)) @@ -972,6 +971,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; /* Prefer peripheral clock which provides higher frequency. */ if (gd->arch.sdhc_per_clk) cfg->sdhc_clk = gd->arch.sdhc_per_clk; |