diff options
author | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /drivers/mmc | |
parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
parent | fe33066d246462551f385f204690a11018336ac8 (diff) |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/Kconfig | 14 | ||||
-rw-r--r-- | drivers/mmc/fsl_esdhc_imx.c | 2 | ||||
-rw-r--r-- | drivers/mmc/fsl_esdhc_spl.c | 18 | ||||
-rw-r--r-- | drivers/mmc/gen_atmel_mci.c | 8 | ||||
-rw-r--r-- | drivers/mmc/sh_sdhi.c | 2 |
5 files changed, 29 insertions, 15 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index bf4d994ff69..878f867c627 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -385,6 +385,11 @@ config MMC_OMAP36XX_PINS If unsure, say N. +config HSMMC2_8BIT + bool "Enable 8-bit interface for eMMC (interface #2)" + depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ + AM43XX || ARCH_KEYSTONE) + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on ARCH_RMOBILE @@ -820,8 +825,13 @@ config MMC_MTK endif +config FSL_SDHC_V2_3 + bool + config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" + select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \ + || ARCH_C29X help This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. @@ -881,6 +891,10 @@ config FSL_USDHC help This enables the Ultra Secured Digital Host Controller enhancements +config FSL_ESDHC_PIN_MUX + bool "Perform esdhc device-tree fixup" + depends on (FSL_ESDHC || FSL_ESDHC_IMX) && OF_LIBFDT + endmenu config SYS_FSL_ERRATUM_ESDHC111 diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 5ee3ce78231..66caf683f74 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1360,7 +1360,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) #if CONFIG_IS_ENABLED(OF_LIBFDT) __weak int esdhc_status_fixup(void *blob, const char *compat) { - if (IS_ENABLED(FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { + if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", sizeof("disabled"), 1); return 1; diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index aa00d7e2014..6d7c0cff22a 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -9,7 +9,7 @@ #include <mmc.h> #include <malloc.h> -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS extern uchar mmc_u_boot_offs[]; #endif @@ -97,7 +97,7 @@ void __noreturn mmc_boot(void) } #ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + offset = CFG_SYS_MMC_U_BOOT_OFFS; #else sector = 0; again: @@ -153,16 +153,16 @@ again: val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE; #else - offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + offset += CFG_SYS_MMC_U_BOOT_OFFS; #endif #endif /* * Load U-Boot image from mmc into RAM */ - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; + code_len = CFG_SYS_MMC_U_BOOT_SIZE; blk_start = offset / mmc->read_bl_len; blk_off = offset % mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; @@ -176,7 +176,7 @@ again: blk_start++; } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (uchar *)CFG_SYS_MMC_U_BOOT_DST + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); @@ -189,18 +189,18 @@ again: * after SDHC DMA transfer. */ if (blk_off) - memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST, tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE); /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + uboot = (void *)CFG_SYS_MMC_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 607a22368cb..d91819acfd7 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -24,8 +24,8 @@ #include <asm/arch/hardware.h> #include "atmel_mci.h" -#ifndef CONFIG_SYS_MMC_CLK_OD -# define CONFIG_SYS_MMC_CLK_OD 150000 +#ifndef CFG_SYS_MMC_CLK_OD +# define CFG_SYS_MMC_CLK_OD 150000 #endif #define MMC_DEFAULT_BLKLEN 512 @@ -448,9 +448,9 @@ static int mci_init(struct mmc *mmc) /* Set default clocks and blocklen */ #ifdef CONFIG_DM_MMC - mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #else - mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #endif return 0; diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index b2d0fac9636..3ce7cbf71f8 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -761,7 +761,7 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) struct mmc *mmc; struct sh_sdhi_host *host = NULL; - if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL) + if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL) return -ENODEV; host = malloc(sizeof(struct sh_sdhi_host)); |