diff options
| author | Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | 2022-09-01 15:05:31 +0900 |
|---|---|---|
| committer | Jagan Teki <jagan@edgeble.ai> | 2022-10-23 10:50:17 +0530 |
| commit | 4d60001fdf0c13ab1ccf720bb3cd6e5d385386bb (patch) | |
| tree | 7ceab529a161667689b40f8e816700b4e0231859 /drivers/mtd/spi/spi-nor-core.c | |
| parent | ee1c709cfde71b339a5c5dd0788522340c4c7e92 (diff) | |
mtd: spi-nor-core: Track flash's internal address mode
The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd/spi/spi-nor-core.c')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f8d56699690..08905a4055f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2238,10 +2238,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: nor->addr_width = 3; + nor->addr_mode_nbytes = 3; break; case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: nor->addr_width = 4; + nor->addr_mode_nbytes = 4; break; default: |