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| author | Tom Rini <trini@konsulko.com> | 2025-10-06 13:20:24 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-10-06 13:20:24 -0600 |
| commit | 0eaa4b337336dbbe93395d1f2ccc18937eaafea2 (patch) | |
| tree | c01e661d69181dceca68f56a4849a9bd04608521 /drivers/net/mdio_mux_meson_gxl.c | |
| parent | e50b1e8715011def8aff1588081a2649a2c6cd47 (diff) | |
| parent | 4e4a9de31de2a5f395ee25c59e4026422fbcb27e (diff) | |
Merge branch 'next'
Merge the outstanding changes from the 'next' branch to master.
Diffstat (limited to 'drivers/net/mdio_mux_meson_gxl.c')
| -rw-r--r-- | drivers/net/mdio_mux_meson_gxl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/mdio_mux_meson_gxl.c b/drivers/net/mdio_mux_meson_gxl.c index 8ef3ae598b7..31898ed437e 100644 --- a/drivers/net/mdio_mux_meson_gxl.c +++ b/drivers/net/mdio_mux_meson_gxl.c @@ -19,6 +19,7 @@ #define REG2_LEDACT GENMASK(23, 22) #define REG2_LEDLINK GENMASK(25, 24) #define REG2_DIV4SEL BIT(27) +#define REG2_REVERSED BIT(28) #define REG2_ADCBYPASS BIT(30) #define REG2_CLKINSEL BIT(31) #define ETH_REG3 0x4 @@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv) * The only constraint is that it must match the one in * drivers/net/phy/meson-gxl.c to properly match the PHY. */ - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), priv->regs + ETH_REG2); /* Enable the internal phy */ |