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| author | Tom Rini <trini@konsulko.com> | 2020-03-02 09:20:12 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-03-02 09:20:12 -0500 |
| commit | bd7bb38699412bf95449bf9f23aa625c0436eae6 (patch) | |
| tree | 4e30bec98504a3923d40df2594b48c173032e192 /drivers/net/phy/dp83867.c | |
| parent | 5045289820835ce0baf5d7cea86f9fdc6170d189 (diff) | |
| parent | 25974079750c5fbf920a226a26d8cb9b1aff2544 (diff) | |
Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx fixes for v2020.04-rc4
- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection
Diffstat (limited to 'drivers/net/phy/dp83867.c')
| -rw-r--r-- | drivers/net/phy/dp83867.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 08935d9c15f..0098997c0cd 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -65,6 +65,7 @@ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 #define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14) #define DP83867_PHYCR_RESERVED_MASK BIT(11) +#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) #define DP83867_MDI_CROSSOVER 5 #define DP83867_MDI_CROSSOVER_MDIX 2 #define DP83867_PHYCTRL_SGMIIEN 0x0800 @@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev) val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); + /* Do not force link good */ + val &= ~DP83867_PHYCR_FORCE_LINK_GOOD; + /* The code below checks if "port mirroring" N/A MODE4 has been * enabled during power on bootstrap. * |