diff options
| author | Tom Rini <trini@konsulko.com> | 2022-04-05 11:27:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-05 11:27:39 -0400 |
| commit | 037ef53cf01c522073a0a930c84c3ca858f032e1 (patch) | |
| tree | aa6ce3d6777690251a57e7bb85c2865005046b30 /drivers/net/phy/phy.c | |
| parent | 4de720e98d552dfda9278516bf788c4a73b3e56f (diff) | |
| parent | a7379ba6505d70d887951be9ebb3f47e3792c708 (diff) | |
Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc1 v2
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
Diffstat (limited to 'drivers/net/phy/phy.c')
| -rw-r--r-- | drivers/net/phy/phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 92fff5b72c0..d4731860f73 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1049,7 +1049,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, #ifdef CONFIG_PHY_ETHERNET_ID if (!phydev) - phydev = phy_connect_phy_id(bus, dev, interface); + phydev = phy_connect_phy_id(bus, dev, addr, interface); #endif #ifdef CONFIG_PHY_XILINX_GMII2RGMII |