Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT

1 files changed, 10 insertions, 10 deletions

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 6c9f1f7c272..16ba915fbaa 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -14,14 +14,13 @@
 #include <console.h>
 #include <malloc.h>
 #include <asm/global_data.h>
-#include <asm/io.h>
 #include <phy.h>
 #include <miiphy.h>
 #include <fdtdec.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
-#include <asm/io.h>
 #include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -113,12 +112,12 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
 	/* Word aligned buffer, no correction needed. */
 	to32ptr = (u32 *) destptr;
 	while (bytecount > 3) {
-		*to32ptr++ = *from32ptr++;
+		*to32ptr++ = __raw_readl(from32ptr++);
 		bytecount -= 4;
 	}
 	to8ptr = (u8 *) to32ptr;
 
-	alignbuffer = *from32ptr++;
+	alignbuffer = __raw_readl(from32ptr++);
 	from8ptr = (u8 *) &alignbuffer;
 
 	for (i = 0; i < bytecount; i++)
@@ -136,8 +135,7 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
 
 	from32ptr = (u32 *) srcptr;
 	while (bytecount > 3) {
-
-		*to32ptr++ = *from32ptr++;
+		__raw_writel(*from32ptr++, to32ptr++);
 		bytecount -= 4;
 	}
 
@@ -148,7 +146,7 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
 	for (i = 0; i < bytecount; i++)
 		*to8ptr++ = *from8ptr++;
 
-	*to32ptr++ = alignbuffer;
+	__raw_writel(alignbuffer, to32ptr++);
 }
 
 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
@@ -519,6 +517,8 @@ try_again:
 		length = ntohs(ip->ip_len);
 		length += ETHER_HDR_SIZE + ETH_FCS_LEN;
 		debug("IP Packet %x\n", length);
+		if (length > PKTSIZE)
+			length = PKTSIZE;
 		break;
 	default:
 		debug("Other Packet\n");
@@ -527,7 +527,7 @@ try_again:
 	}
 
 	/* Read the rest of the packet which is longer then first read */
-	if (length != first_read)
+	if (length > first_read)
 		xemaclite_alignedread(addr + first_read,
 				      etherrxbuff + first_read,
 				      length - first_read);
@@ -615,8 +615,8 @@ static int emaclite_of_to_plat(struct udevice *dev)
 	int offset = 0;
 
 	pdata->iobase = dev_read_addr(dev);
-	emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
-								 0x10000);
+	emaclite->regs = (struct emaclite_regs *)ioremap(pdata->iobase,
+							 0x10000);
 
 	emaclite->phyaddr = -1;