diff options
| author | Michal Simek <michal.simek@amd.com> | 2024-09-13 09:37:38 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-09-20 15:31:19 +0200 |
| commit | 6161eaf05794ab2fc1af2b0159083ab6b955e20c (patch) | |
| tree | f9c9dc7f5eaaf68ca36a9e76038745cc3e280b44 /drivers/net/zynq_gem.c | |
| parent | 067e0294806eb132e01f64d89a4df9a9cc857692 (diff) | |
net: gem: Remove undocumented is-internal-pcspma dt flag
Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
Diffstat (limited to 'drivers/net/zynq_gem.c')
| -rw-r--r-- | drivers/net/zynq_gem.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index fe7d1084450..461805ae53f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -228,7 +228,6 @@ struct zynq_gem_priv { struct clk tx_clk; struct clk pclk; u32 max_speed; - bool int_pcs; bool dma_64bit; u32 clk_en_info; struct reset_ctl_bulk resets; @@ -504,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev) * Set SGMII enable PCS selection only if internal PCS/PMA * core is used and interface is SGMII. */ - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; } @@ -529,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev) writel(nwcfg, ®s->nwcfg); #ifdef CONFIG_ARM64 - if (priv->interface == PHY_INTERFACE_MODE_SGMII && - priv->int_pcs) { + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { /* * Disable AN for fixed link configuration, enable otherwise. * Must be written after PCS_SEL is set in nwconfig, @@ -992,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev) return -EINVAL; priv->interface = pdata->phy_interface; - priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - priv->clk_en_info = dev_get_driver_data(dev); return 0; |