diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2021-02-09 15:28:15 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-23 14:56:59 +0100 |
| commit | 9b7aac75365b68bae2e8f7cf074ba95638d31882 (patch) | |
| tree | 9d2ee4b001275fe6a2191ead6ec3913e033a783d /drivers/net/zynq_gem.c | |
| parent | 3aba25bc382beeb8a92b46d23fd1db47dfcb1121 (diff) | |
clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/net/zynq_gem.c')
| -rw-r--r-- | drivers/net/zynq_gem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 585c06d6bd8..a2a01112018 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -477,13 +477,13 @@ static int zynq_gem_init(struct udevice *dev) } ret = clk_set_rate(&priv->clk, clk_rate); - if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { + if (IS_ERR_VALUE(ret)) { dev_err(dev, "failed to set tx clock rate\n"); return ret; } ret = clk_enable(&priv->clk); - if (ret && ret != -ENOSYS) { + if (ret) { dev_err(dev, "failed to enable tx clock\n"); return ret; } |