Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.03

- ATF handoff
- DT syncups
- gem: Use wait_for_bit(), add simple clk support
- Simple clk driver for ZynqMP
- Other small changes

2 files changed, 29 insertions, 25 deletions

diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
index f3eaf2e97ce..920bfcb380b 100644
--- a/drivers/net/phy/xilinx_phy.c
+++ b/drivers/net/phy/xilinx_phy.c
@@ -101,11 +101,11 @@ static int xilinxphy_startup(struct phy_device *phydev)
 
 static int xilinxphy_of_init(struct phy_device *phydev)
 {
-	struct udevice *dev = (struct udevice *)&phydev->dev;
 	u32 phytype;
 
 	debug("%s\n", __func__);
-	phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1);
+	phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset,
+				 "phy-type", -1);
 	if (phytype == XAE_PHY_TYPE_1000BASE_X)
 		phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
 
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index d2e5e7c7cd1..6dd87cf28f9 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -9,6 +9,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <clk.h>
 #include <common.h>
 #include <dm.h>
 #include <net.h>
@@ -181,35 +182,22 @@ struct zynq_gem_priv {
 	struct phy_device *phydev;
 	int phy_of_handle;
 	struct mii_dev *bus;
+#ifdef CONFIG_CLK_ZYNQMP
+	struct clk clk;
+#endif
 };
 
-static inline int mdio_wait(struct zynq_gem_regs *regs)
-{
-	u32 timeout = 20000;
-
-	/* Wait till MDIO interface is ready to accept a new transaction. */
-	while (--timeout) {
-		if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
-			break;
-		WATCHDOG_RESET();
-	}
-
-	if (!timeout) {
-		printf("%s: Timeout\n", __func__);
-		return 1;
-	}
-
-	return 0;
-}
-
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 			u32 op, u16 *data)
 {
 	u32 mgtcr;
 	struct zynq_gem_regs *regs = priv->iobase;
+	int err;
 
-	if (mdio_wait(regs))
-		return 1;
+	err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+			    true, 20000, true);
+	if (err)
+		return err;
 
 	/* Construct mgtcr mask for the operation */
 	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
@@ -219,8 +207,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
 	/* Write mgtcr and wait for completion */
 	writel(mgtcr, &regs->phymntnc);
 
-	if (mdio_wait(regs))
-		return 1;
+	err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+			    true, 20000, true);
+	if (err)
+		return err;
 
 	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
 		*data = readl(&regs->phymntnc);
@@ -469,8 +459,14 @@ static int zynq_gem_init(struct udevice *dev)
 
 	/* Change the rclk and clk only not using EMIO interface */
 	if (!priv->emio)
+#ifndef CONFIG_CLK_ZYNQMP
 		zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
 					ZYNQ_GEM_BASEADDR0, clk_rate);
+#else
+		ret = clk_set_rate(&priv->clk, clk_rate);
+		if (IS_ERR_VALUE(ret))
+			return -1;
+#endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -643,6 +639,14 @@ static int zynq_gem_probe(struct udevice *dev)
 	priv->tx_bd = (struct emac_bd *)bd_space;
 	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 
+#ifdef CONFIG_CLK_ZYNQMP
+	ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
+	if (ret < 0) {
+		dev_err(dev, "failed to get clock\n");
+		return -EINVAL;
+	}
+#endif
+
 	priv->bus = mdio_alloc();
 	priv->bus->read = zynq_gem_miiphy_read;
 	priv->bus->write = zynq_gem_miiphy_write;