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| author | Tom Rini <trini@konsulko.com> | 2021-03-15 12:15:38 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-03-15 12:15:38 -0400 |
| commit | 22fc991dafee0142fc6bf621e7bd558bd58020b4 (patch) | |
| tree | e5da8826fd735de968519f432864dc1545d96017 /drivers/pci/pci-aardvark.c | |
| parent | 1876b390f31afca15de334e499aa071b0bf64a44 (diff) | |
| parent | 4103e13534141c31e4e9bf40848ab3a61dabce81 (diff) | |
Merge tag 'v2021.04-rc4' into next
Prepare v2021.04-rc4
Diffstat (limited to 'drivers/pci/pci-aardvark.c')
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b4e1b602405..3b9309f52c5 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -105,6 +105,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | |