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authorTom Rini <trini@konsulko.com>2025-04-24 10:46:17 -0600
committerTom Rini <trini@konsulko.com>2025-04-24 10:46:17 -0600
commit10f48365112b164bee6564033ab682747efcb483 (patch)
tree89bf3ab57fb9bd2f96376105629e6429d1533f34 /drivers/pci/pcie_cdns_ti.c
parent629f089387adf7b0c39b77ac8d337cff7989f81d (diff)
parentf4baa55c5bee5a2eaedf80c8a84cc839230a9a73 (diff)
Merge patch series "Add PCIe support for TI AM64 SoC"
Hrushikesh Salunke <h-salunke@ti.com> says: TI's AM64 SoC has a single instance of Cadence PCIe Controller. This series enables support for PCIe in AM64 SoC and to configure it in Root-Complex mode of operation. Link: https://lore.kernel.org/r/20250416120830.138965-1-h-salunke@ti.com
Diffstat (limited to 'drivers/pci/pcie_cdns_ti.c')
-rw-r--r--drivers/pci/pcie_cdns_ti.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c
index 41469a186a3..9d1d123a18c 100644
--- a/drivers/pci/pcie_cdns_ti.c
+++ b/drivers/pci/pcie_cdns_ti.c
@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/log2.h>
+#include <linux/sizes.h>
#include <power-domain.h>
#include <regmap.h>
#include <syscon.h>
@@ -834,11 +835,21 @@ static const struct pcie_cdns_ti_data j7200_pcie_rc_data = {
.max_lanes = 2,
};
+static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
+ .mode = PCIE_MODE_RC,
+ .quirk_detect_quiet_flag = true,
+ .max_lanes = 1,
+};
+
static const struct udevice_id pcie_cdns_ti_ids[] = {
{
.compatible = "ti,j7200-pcie-host",
.data = (ulong)&j7200_pcie_rc_data,
},
+ {
+ .compatible = "ti,am64-pcie-host",
+ .data = (ulong)&am64_pcie_rc_data,
+ },
{},
};