diff options
| author | Tom Rini <trini@konsulko.com> | 2021-05-12 10:07:21 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-05-12 10:07:21 -0400 |
| commit | ea184cbff99ea1d82dcf94c95afe054e95da5069 (patch) | |
| tree | 48553e6cf25f0b5f34483c3fddafdebbbc240b55 /drivers/ram/k3-ddrss/lpddr4_structs_if.h | |
| parent | 59a2b9e605c5a5e2dff35506a13b51f33d3051b4 (diff) | |
| parent | bbc9da58b332bd44e51ac5579040ea984b2f963b (diff) | |
Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
Diffstat (limited to 'drivers/ram/k3-ddrss/lpddr4_structs_if.h')
| -rw-r--r-- | drivers/ram/k3-ddrss/lpddr4_structs_if.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h new file mode 100644 index 00000000000..e41cbb7ff48 --- /dev/null +++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2021 Cadence Design Systems, Inc. + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_STRUCTS_IF_H +#define LPDDR4_STRUCTS_IF_H + +#include <linux/types.h> +#include "lpddr4_if.h" + +struct lpddr4_config_s { + struct lpddr4_ctlregs_s *ctlbase; + lpddr4_infocallback infohandler; + lpddr4_ctlcallback ctlinterrupthandler; + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +struct lpddr4_privatedata_s { + struct lpddr4_ctlregs_s *ctlbase; + lpddr4_infocallback infohandler; + lpddr4_ctlcallback ctlinterrupthandler; + lpddr4_phyindepcallback phyindepinterrupthandler; +}; + +struct lpddr4_debuginfo_s { + u8 pllerror; + u8 iocaliberror; + u8 rxoffseterror; + u8 catraingerror; + u8 wrlvlerror; + u8 gatelvlerror; + u8 readlvlerror; + u8 dqtrainingerror; +}; + +struct lpddr4_fspmoderegs_s { + u8 mr1data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr2data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr3data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr11data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr12data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr13data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr14data_fn[LPDDR4_INTR_MAX_CS]; + u8 mr22data_fn[LPDDR4_INTR_MAX_CS]; +}; + +#endif /* LPDDR4_STRUCTS_IF_H */ |