diff options
| author | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
| commit | 21e25992c86306b41caafcf85efc47d66f5efa6e (patch) | |
| tree | 3c9f1ccb01f1a83f077064b4e4f4e028760f2e39 /drivers/ram/stm32mp1/stm32mp1_ddr.c | |
| parent | b4eb57766314062e3dd1ee8e439d2cb2d5dc33d8 (diff) | |
| parent | e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7 (diff) | |
Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ddr.c')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ddr.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 528a171b454..ab913a68761 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -653,10 +653,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } -static void stm32mp1_asr_enable(struct ddr_info *priv) +static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl) { struct stm32mp1_ddrctl *ctl = priv->ctl; + /* SSR is the best we can do. */ + if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE)) + return; + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, RCC_DDRITFCR_DDRCKMOD_ASR); @@ -666,8 +670,12 @@ static void stm32mp1_asr_enable(struct ddr_info *priv) writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), &ctl->pwrtmg); + + /* HSR we can do. */ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); - setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */ + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); wait_sw_done_ack(ctl); @@ -845,7 +853,7 @@ start: config->c_reg.pwrctl); /* Enable auto-self-refresh, which saves a bit of power at runtime. */ - stm32mp1_asr_enable(priv); + stm32mp1_asr_enable(priv, config->c_reg.pwrctl); /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); |