diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
| commit | 2f7821a9278e710b2e825018303c2942f920a77d (patch) | |
| tree | 8e4d97bcd17960370457134c0770276e5fecc209 /drivers/ram/stm32mp1/stm32mp1_ram.c | |
| parent | a9e90d357bbf539e07c1d971161e027eb335183e (diff) | |
| parent | eae488b77906692627622abc61f5b7160b6eb2a4 (diff) | |
Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ram.c')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ram.c | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 49b1262461b..a6c19af9722 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width) reg = readl(&ctl->addrmap3); /* addrmap3.addrmap_col_b6 */ - val = (reg & GENMASK(3, 0)) >> 0; + val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap3.addrmap_col_b7 */ - val = (reg & GENMASK(11, 8)) >> 8; + val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++; /* addrmap3.addrmap_col_b8 */ - val = (reg & GENMASK(19, 16)) >> 16; + val = (reg & GENMASK(20, 16)) >> 16; if (val <= 7) bits++; /* addrmap3.addrmap_col_b9 */ - val = (reg & GENMASK(27, 24)) >> 24; + val = (reg & GENMASK(28, 24)) >> 24; if (val <= 7) bits++; reg = readl(&ctl->addrmap4); /* addrmap4.addrmap_col_b10 */ - val = (reg & GENMASK(3, 0)) >> 0; + val = (reg & GENMASK(4, 0)) >> 0; if (val <= 7) bits++; /* addrmap4.addrmap_col_b11 */ - val = (reg & GENMASK(11, 8)) >> 8; + val = (reg & GENMASK(12, 8)) >> 8; if (val <= 7) bits++; @@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) reg = readl(&ctl->addrmap6); /* addrmap6.addrmap_row_b12 */ val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b13 */ val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b14 */ val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 7) + if (val <= 11) bits++; /* addrmap6.addrmap_row_b15 */ val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 7) + if (val <= 11) bits++; + if (reg & BIT(31)) + printf("warning: LPDDR3_6GB_12GB is not supported\n"); + return bits; } @@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = { .get_info = stm32mp1_ddr_get_info, }; +static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = { + .nb_bytes = 2, +}; + static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = { .nb_bytes = 4, }; static const struct udevice_id stm32mp1_ddr_ids[] = { { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg}, + { .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg}, { } }; |