diff options
| author | Marek Vasut <marek.vasut@mailbox.org> | 2025-05-12 19:09:05 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2025-06-11 09:42:56 +0200 |
| commit | 447d1bd05acbfb155abe66514d71629f11fb3927 (patch) | |
| tree | b04cac97e3eae75c7a96f7f64089790271b9f9d0 /drivers/ram/stm32mp1/stm32mp1_ram.c | |
| parent | 0298696b1efcbaf05317e5559bdc99cbac36293c (diff) | |
ram: stm32mp1: Add STM32MP13xx support
Add support for configuring DRAM controller on STM32MP13xx SoC.
The DRAM controller is basically identical to the DWC controller
on STM32MP15xx SoC, except the bus width is reduced from 32bit to
16bit and a few registers and bits are therefore not present.
Handle the difference by factoring these parts out. Use IS_ENABLE()
as much as possible to assure code which is not enabled on builds
for a single SoC gets compiled out. Handle the different offset of
RCC_DDRITFCR register and missing DDRC2 clock the same way.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ram.c')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ram.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index e9cd6229ec4..5f9b91d50e4 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -33,6 +33,7 @@ static const char *const clkname[] = { int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) { + bool is_mp13 = is_stm32mp13_ddrc(priv); unsigned long ddrphy_clk; unsigned long ddr_clk; struct clk clk; @@ -40,6 +41,10 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) unsigned int idx; for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { + /* DDRC2 clock are available only on STM32MP15xx */ + if (is_mp13 && !strcmp(clkname[idx], "ddrc2")) + continue; + ret = clk_get_by_name(priv->dev, clkname[idx], &clk); if (!ret) |