diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-10 14:09:23 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2019-05-23 11:38:10 +0200 |
| commit | c60fed14f64ac82721ef9afc6ac47e0379538900 (patch) | |
| tree | d5dbeed0f9ff972784b7e320414755e7c5d4a6ff /drivers/ram/stm32mp1/stm32mp1_ram.c | |
| parent | 0cb1aa94093c22dd5b3dce32d371e154abc06ffe (diff) | |
stm32mp1: ram: change ddr speed to kHz
Allow fractional support in DDR tools.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_ram.c')
| -rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_ram.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index e45a3b2658a..d04c6aa6b10 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -20,7 +20,7 @@ static const char *const clkname[] = { "ddrphyc" /* LAST clock => used for get_rate() */ }; -int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) +int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) { unsigned long ddrphy_clk; unsigned long ddr_clk; @@ -43,13 +43,13 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) priv->clk = clk; ddrphy_clk = clk_get_rate(&priv->clk); - debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", - mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); + debug("DDR: mem_speed (%d kHz), RCC %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); /* max 10% frequency delta */ - ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); - if (ddr_clk > (mem_speed * 1000 * 100)) { - pr_err("DDR expected freq %d MHz, current is %d MHz\n", - mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); + ddr_clk = abs(ddrphy_clk - mem_speed * 1000); + if (ddr_clk > (mem_speed * 100)) { + pr_err("DDR expected freq %d kHz, current is %d kHz\n", + mem_speed, (u32)(ddrphy_clk / 1000)); return -EINVAL; } |